1. Field
The present disclosure generally relates to receiver circuits. More specifically, the present disclosure relates to a receiver circuit that performs clock-data-recovery error detection, which is suitable for use in high-speed links.
2. Related Art
To reduce overhead in many communication systems, clock signals are often encoded in the data signals that are transmitted across a communication channels by a transmitter circuit. These clock signals are subsequently recovered from the data signals in a receiver circuit using a clock-data-recovery (CDR) circuit. In the CDR circuit, the phase or skew of the recovered sampling clock is typically adjusted so that the data signals are sampled in the middle of a unit- or bit-time interval. This data-sampling position often provides improved performance and robustness against noise and jitter in the data signals.
However, in high-speed serial links it can be difficult to adjust the skew of the sampling clock so that the data signals are sampled in the middle of the bit-time interval. At lower data rates, the data signals can be oversampled. Because oversampling produces multiple data samples, it is easier to adjust the skew of the sampling clock so that the data signals are sampled at the center and the edge of the bit-time interval. However, as the data rate is increased, oversampling is typically impractical because of increased power consumption. Consequently, at high data rates (such as 10 Gbps), baud-rate sampling is often used (i.e., one data sample per bit-time interval), which can make it more difficult to adjust the skew of the sampling clock.
Furthermore, at high data rates there are often channel-dependent effects, such as intersymbol interference (ISI), which degrade the performance when the data signals are sampled in the middle of the bit-time interval. For example, the optimal data-sampling position may be earlier or later than the middle of the bit-time interval. However, it can be difficult to determine the optimal skew of the sampling clock in the presence of such channel-dependent effects, especially as a function of voltage and temperature.
In order to improve performance, some systems include feed-forward equalizers that modify the data signals to change the data-sampling position. However, if a feed-forward equalizer is implemented in a receiver circuit, there is often an adverse impact on: the signal-to-noise ratio (and, thus, the system performance), the power consumption, and the receive-circuit area (and, thus, on the cost). Alternatively, if a feed-forward equalizer is implemented in a transmitter circuit, it can adversely impact the signal-to-noise ratio (and, thus, the system performance).
Hence, what is needed is a receiver circuit and an associated system that does not suffer from the above-described problems.